This invention concerns a three-input binary adder cell with high-speed sum propagation, of integrated circuit design.
It is well known that high-speed carry adder cells are commonly used in the design of integrated multipliers or adders. However, adder cells with high-speed sum propagation, that is to say in which propagation of the sum is favoured with respect to that of the carry, can be especially interesting for example in integrated multipliers of the "pipe-line" type, or serial adding type. This type of multiplier, controlled by a clock and therefore synchronous, produces the partial products from the right to the left, that is to say from the bits of the lowest order toward the highest-order bits, exactly as in manual multiplication, the shift of a supplementary power of two occurring on each clock pulse. This type of multiplier is much slower than the so-called parallel integrated multipliers in which information is propagated asynchronously, but it reduces by a factor of about ten the silicon surface required to produce it with respect to the silicon surface required to produce a parallel miltiplier of the same capacity.